1. Field of the Invention
The present invention relates generally to a nonvolatile semiconductor memory and a method for controlling the same and more particularly to a nonvolatile semiconductor memory that performs writing and erasing in units of a plurality of memory cells (data) and a method for controlling the same.
2. Description of Related Art
Electrically Erasable and Programmable ROM (EEPROM) is widely known as a nonvolatile memory which is electrically erasable and programmable. A flash memory, which is one type of EEPROM and erasable in units of blocks, has a significantly increasing memory capacity and gains attention as a memory to substitute for a disc or the like.
In the flash memory, a memory cell is composed of a transistor having a floating gate and a control gate. Data is recorded by electrically writing data on the memory cell transistor. Data is erased by electrically erasing data on the memory cell transistor.
In the electrical writing on the memory cell transistor, a high voltage for writing is applied to the control gate and the drain of the memory cell transistor. Electrons are thereby injected to the floating gate, setting a threshold of the memory cell transistor to be higher.
For example, as shown in FIG. 17, a flash memory which switches the threshold of the memory cell transistor between two levels by one-time electrical writing and stores the data of “0” and “1” in one memory cell transistor is called a binary flash memory. As shown in FIG. 18, a flash memory which switches the threshold of the memory cell transistor among a plurality of levels by a plurality of times of electrical writing and stores a plurality of data segments such as the data of “0”, “1”, “2” and “3” in one memory cell transistor is called a multivalued flash memory. Though the use of the multivalued flash memory allows an increase in memory capacity, it increases the number of writing times accordingly. For instance, the flash memory of FIG. 18 requires three times of writing in order to change the state of the memory cell transistor from the state storing the data “3” to the state storing the data “0”.
Further, after writing data to the memory cell transistor, the read operation called “verify” is performed in order to verify that the threshold of the memory cell transistor reaches a target value. Thus, the data write operation is implemented by automatically repeating the electrical writing and the verify operation (automatic writing) and it is necessary to provide a device for controlling the repetition for every target memory cell. Similarly in the data erase operation, it is necessary to provide an automatic erase control device which automatically repeats the electrical erasing and the verify operation for every target memory cell.
In this way, recording and erasing of data on the flash memory requires sequence control such as automatic writing or automatic erasing. Reduction of the processing time by using a suitable flow is one factor to determine the commercial value.
FIG. 19 shows the structure of a nonvolatile semiconductor memory of a related art. As shown in FIG. 19, the nonvolatile semiconductor memory includes a buffer 901 that latches an external address or external data supplied from outside, a sequence controller 904 that controls a write sequence, a memory cell array 907 that has memory cells arranged in array, a read circuit 905 that reads data from the memory cell array 907, a write circuit 906 that writes data to the memory cell array 907, and a comparator 909 that compares the data read from the memory cell array 907 with external data.
The flowchart of FIG. 20 shows an automatic write operation in the nonvolatile semiconductor memory of a related art. The automatic write operation is implemented by the control of the sequence controller 904.
Initially, one external address and one external data to be written are input as a command through an external bus or the like and stored in the buffer 901 (S901). Then, the read circuit 905 performs the read operation on the memory cell of the memory cell array 907 which is specified by the external address under the control of the sequence controller 904 (S902). Then, the comparator 909 determines whether the read data corresponds to the input external data (S903). The process of the steps S902 and S903 is the verify operation.
If it is determined in the step S903 that the data correspond to each other, the sequence controller 904 terminates the automatic write operation. If, on the other hand, it is determined in the step S903 that the data does not correspond, the write circuit 906 performs the write operation of the external data into the memory cell of the memory cell array 907 which is specified by the external address under the control of the sequence controller 904 (S904). After that, the process further performs the verify operation (S902 and S903), and repeats the write operation and the verify operation until the data of the memory cell corresponds to the external data.
Japanese Unexamined Patent Application Publications Nos. 2002-366420 and H6-195989 include the disclosure concerning a nonvolatile semiconductor memory. The technique disclosed therein sets a flag that indicates the completion of erasing for each block or sector.
However, since the conventional nonvolatile semiconductor memory inputs a command (one address and one data) from the outside with respect to each writing or erasing on one address, it has a disadvantage of a low processing efficiency of writing or erasing to take a long time for the write and erase operation.
FIG. 21 shows the operation of writing a plurality of data segments in chronological order in the conventional nonvolatile semiconductor memory. This is the case where the verify succeeds in one-time writing.
In order to write first data, the operation first inputs one address and one data in T101. Then, it performs the verify before writing (pre-verify) in T102, writes one data in the memory cell of one address in T103, and then performs the verify after writing (post-verify) in T104. The writing of the first data thereby completes. Then, in order to write second data, the operation further inputs one address and one data and writes the data in the same manner as above. The operation of T101 to T104 is repeated for the number of data segments to be written.
Therefore, even in the case where it is possible to identify other addresses with one address such as when writing a large amount of data to successive addresses, it is necessary to input an address and data each time for every address of data to be written, thus forcing to perform the input operation in vain.
External commands are input from CPU or the like through a bus. With the recent increase in processing speed of CPU and bus, transfer speed and capacity, a large amount of successive data segments are input in many cases. Thus, the useless processing for each address causes significant deterioration in the overall efficiency and processing time of the data write or erase operation.